1. Field of the Invention
The present invention relates to semiconductor devices. More particularly, the present invention relates to a low-voltage punch-through transient suppressor employing a dual base structure.
2. The Prior Art
Electronic circuitry which is designed to operate at supply voltages less than 5 volts are extremely susceptible to damage from overvoltage conditions caused by electrostatic discharge, inductively coupled spikes, or other transient conditions from its operating environment. The current trend of the reduction in circuit operating voltage dictates a corresponding reduction in the maximum voltage that the circuitry can withstand without incurring damage. As operating voltages drop below 5 volts to 3.3 volts and below it becomes necessary to clamp transient voltage excursions to below five volts.
The most widely used device currently in use for low voltage protection is the reversed biased p+n+ zener diode. See O. M. Clark, xe2x80x9cTransient voltage suppressor types and applicationxe2x80x9d, IEEE Trans Power Electron., vol. 5, pp. 20-26, November 1990. These devices perform well at voltages of 5 volts and above but run into problems when scaled to clamp below 5 volts. The two major drawbacks incurred by using this device structure are very large leakage currents and high capacitance. These detrimental characteristics increase power consumption and restrict operating frequency.
A second device capable low clamping voltages is the n+pn+ uniform base punch through diode, such as disclosed in P. J. Kannam, xe2x80x9cDesign concepts of high energy punch-through structuresxe2x80x9d IEEE Trans. Electron Devices, ED-23, no. 8, pp. 879-882, 1976, and D. de Cogan, xe2x80x9cThe punch through diodexe2x80x9d, Microelectronics, vol. 8, no. 2, pp. 20-23, 1977. These devices exhibit much improved leakage and capacitance characteristics over the conventional pn diode but suffer from poor clamping characteristics at high currents. If the designer tries to improve clamping to protect circuitry under industry standard surge conditions by increasing die area, the results are devices which are too large to produce economically.
It is therefore an object of the present invention to provide a low-voltage transient suppressor which avoids some of the shortcomings of the prior art.
It is another object of the present invention to provide a low-voltage transient suppressor which has a low leakage current.
It is further object of the present invention to provide a low-voltage transient suppressor which has a lower capacitance than prior-art low-voltage transient suppressors.
It is yet another object of the present invention to provide a low-voltage transient suppressor which has improved high-current clamping characteristics compared to prior-art low-voltage transient suppressors.
The transient suppressor device of the present invention comprises a n+pxe2x88x92p+n+ punch-through diode. It is a device which can clamp at low voltages and have leakage and capacitance characteristics superior to those of prior-art transient suppressors. The punch-through diode of the present invention includes a first region comprising an n+ region, a second region comprising a pxe2x88x92 region abutting the first region, a third region comprising a p+ region abutting the second region, and a fourth region comprising an n+ region abutting the third region.
The peak dopant concentration of the n+ layers should be about 1.5E18 cmxe2x88x923, the peak dopant concentration of the p+ layer should be between about 50 to about 2,000 times the peak concentration of the pxe2x88x92 layer, and the dopant concentration of the pxe2x88x92 layer should be between about 0.5E14 cmxe2x88x923 and about 1.0E17 cmxe2x88x923. The junction depth of the fourth (n+) region should be between about 0.3 um and about 1.5 um. The thickness of the third (p+) region should be between about 0.3 um and about 2.0 um, and the thickness of the second (pxe2x88x92) region should be between about 0.5 um and about 5.0 um.